Successive-Approximation-Register (SAR) type analog-to-digital converters (ADCs) are widely used in many applications. A schematic diagram of a conventional N-bit SAR ADC 100 is depicted in FIG. 1. ADC 100 converts an analog input signal VIN into a digital output data D and comprises: N capacitors 101, 102, . . . , 105 having capacitances CN−1, CN−2, . . . , C0, respectively, an additional capacitor 106 having capacitance C0 wherein all top plates of the N capacitors 101, 102, . . . , 105 and the additional capacitor 106 are tied together to a common circuit node 121; a switch 120 for connecting the common circuit node 121 to a ground node upon insertion of a sampling signal SAMP; N single pole triple throw (SPTT) switches 111, 112, . . . , 115 for respectively connecting the bottom plates of the N capacitors 101, 102, . . . , 105 to one of the analog input signal VIN, a positive reference voltage VR, and a negative reference voltage −VR; a single pole double throw (SPDT) switch 116 for connecting the bottom plate of the additional capacitor 106 to either the analog input signal VIN or the negative reference voltage −VR; a comparator 130 for comparing a voltage VX of the common circuit node 121 with the ground potential and outputting a binary decision Q; and a SAR logic 140 for receiving the binary decision Q and outputting the sampling signal SAMP and a plurality of control bits to control SPTT 111, 112, . . . , 115 and SPDT 116.
Every SPTT receives a respective control bit bn, for n=N−1, N−2, . . . , 0. For instance, SPTT 111 receives bN−1, SPTT 113 receives b2, and SPTT 115 receives b0. For each SPTT, the bottom plate of the corresponding capacitor will be connected to the analog input signal VIN if the sampling signal SAMP is asserted, will be connected to the positive reference voltage VR if the sampling signal SAMP is not asserted and the corresponding control bit is 1, and will be connected to the negative reference voltage −VR if the sampling signal SAMP is not asserted and the corresponding control bit is 0. For instance, the bottom plate of capacitor 102 will be connected to the analog input signal VIN if the sampling signal SAMP is asserted, will be connected to the positive reference voltage VR if the sampling signal SAMP is not asserted and bN−2 is 1, and will be connected to the negative reference voltage −VR if the sampling signal SAMP is not asserted and bN−2 is 0. For SPDT 116, the bottom plate of capacitor 106 will be connected to the analog input signal VIN if the sampling signal SAMP is asserted, otherwise it will be connected to the negative reference voltage −VR.
In performing an analog-to-digital conversion, the SAR logic 140 first asserts the sampling signal SAMP to connect the bottom plates of all capacitors (i.e., 101, 102, . . . , 106) to the analog input signal VIN and connect the top plates of all capacitors to the ground node to effectively sample the analog input signal VIN onto all of the capacitors. Then it de-asserts the sampling signal SAMP and commences a process of successive approximation to determine optimum values for all control bits bn to make the voltage VX progressively approach the ground potential. The successive approximation is an iteration process, starting from resolving the MSB (most significant bit) bN−1 and ending at resolving the LSB (least significant bit) b0. The initial value is 0 for all control bits. When resolving bit bn in a present iteration, the SAR logic 140 first set bn to 1, then it waits for the comparator 130 to output the binary decision Q. If the binary decision Q is 1, it lets bn stay at 1 and it moves on to the next iteration to resolve the next bit bn−1; otherwise, it toggles bn to 0 and moves on to the next iteration to resolve the next bit bn−1. Once all iterations are done, the SAR logic 140 outputs the final values of the control bits bn as the digital output data D.
In the illustrated prior art ADC 100, the capacitances C0, C1, C2, . . . , CN−1 are chosen to form a sequence of power of two, i.e. Cn=2nCo, therefore the weights of the respective control bit bn also form a sequence of power of two. Prior art ADC 100 is vulnerable to dynamic errors due to factors such as: incomplete settling of VX during an iteration, thermal noise, and so on. Once an incorrect resolution on bn has been made in a present iteration, it moves on to the next iteration to resolve less significant bits and there is no chance to correct the error made in the preset iteration.
Liu et al disclose a method (in “A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration,” IEEE Journal of Solid-State Circuits, VOL. 46. NO. 11, November 2011, pages 2661-2672) to make an incorrect resolution made in a present iteration correctable by later iterations by using a sub-radix-2 DAC, wherein the capacitors are scaled by a factor less than two. The method disclosed by Liu also facilitates the conversion speed by assisting the comparator to resolve the comparison faster by introducing a dynamic threshold. The details are not explained here, and interested readers are recommended to directly read the cited paper to acquire a thorough understanding. A drawback of the disclosed method is that it needs a few extra capacitors and also it needs more elaborate processing. In addition, Liu also proposes a background calibration method to calibrate an error in the digital output data D due to mismatch in the capacitances. However, elaborate or extensive processing is needed for the calibration.
What is disclosed in this application is a method for allowing the SAR ADC to correct an incorrect resolution made in a previous iteration and also facilitating the conversion without requiring extra capacitors or elaborate processing.
Also disclosed is a method to calibrate the SAR ADC.